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3.2.57. c10, TLB preload operation

The TLB preload operations are used to load entries into either the instruction or data TLB as specified by the virtual address. The operation performs a TLB lookup to determine if the virtual address has been cached in the TLB array. If the TLB lookup misses in the TLB array, a hardware translation table walk is performed. There are two possible results of the hardware translation table walk:

  • the descriptor is cached in the TLB array at the entry specified by the Victim field in the TLB Lockdown Register

  • the descriptor faults.

If the operation is a preload D-TLB instruction and the descriptor faults, a data abort is indicated. The DFSR and DFAR indicate the fault type and the fault address, respectively.

If the operation is a preload I-TLB instruction and the descriptor faults, a data abort is indicated. The DFSR indicates the instruction cache maintenance fault value. The DFAR contains the faulty virtual address, and the IFSR contains the fault type encoding.

The TLB preload operations are:

  • accessible in privileged modes only, User mode causes Undefined Instruction exception

  • supported in both Secure and Nonsecure states

  • when CP15 c1 M-bit [0] is LOW, the instruction executes as a NOP

  • when CP15 c1 A-bit [1] is HIGH, no alignment faults are generated as VA[1:0] are ignored.

The data and instruction TLB preload operations are as follows:

MCR p15, 0, <Rd>, c10, c1, 0 ; Data TLB preload operation
MCR p15, 0, <Rd>, c10, c1, 1 ; Instruction TLB preload operation

The TLB preload operation and the TLB lockdown operation can be used to lock entries into the TLB array. Example 3.1 is a code sequence that locks an entry into the TLB array.


This example assumes that the FCSE PID Register is set to 0. If the FCSE PID is not 0, then the MVA of the TLB entry must be invalidated.

LDR r1,=VA              ; Address of entry to lock
MCR p15,0,r1,c8,c5,1    ; Invalidate TLB entry corresponding to VA
LDR r0,=0x00000001      ; base=victim=0 (protect bit=1 [lock])
LDR r2,=0x08400000      ; base=victim=1 (protect bit=0 [unlock])
MCR p15,0,r0,c10,c0,1   ; Write I-TLB Lockdown Register
MCR p15,0,r1,c10,c1,1   ; Prefetch I-TLB
MCR p15,0,r2,c10,c0,1   ; Write I-TLB Lockdown Register