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3.2.61. c11, PLE Channel Number Register

The purpose of the PLE Channel Number Register is to select a PLE channel.

The PLE Channel Number Register is:

  • a read/write register common to Secure and Nonsecure states

  • accessible in User and privileged modes.

Figure 3.55 shows the bit arrangement of the PLE Channel Number Register.

Figure 3.55. PLE Channel Number Register format

Figure 3.55. PLE Channel Number Register format

Table 3.123 shows how the bit values correspond with the PLE Channel Number Register functions.

Table 3.123. PLE Channel Number Register bit functions

Reserved. UNP, SBZ.


Indicates PLE channel selected:

0 = PLE channel 0 selected, reset value

1 = PLE channel 1 selected.

Access in the Nonsecure state depends on the PLE bit, see c1, Nonsecure Access Control Register. The processor can access this register in User mode if the U bit for any channel is set to 1, see c11, PLE User Accessibility Register.

Table 3.124 shows the results of attempted access for each mode.

Table 3.124. Results of access to the PLE User Accessibility Register[50]
  Secure privilegedNonsecure privilegedSecure UserNonsecure User
U bit PLE bitReadWriteReadWriteReadWriteReadWrite

[50] An entry of Undefined in the table means that the access gives an Undefined Instruction exception when the coprocessor instruction is executed.

To access the PLE Channel Number Register, read or write CP15 with:

MRC p15, 0, <Rd>, c11, c2, 0 ; Read PLE Channel Number Register
MCR p15, 0, <Rd>, c11, c2, 0 ; Write PLE Channel Number Register
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