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3.2.59. c11, PLE Identification and Status Registers

The purpose of the PLE Identification and Status Registers is to define:

  • the PLE channels that are physically implemented on the particular device

  • the current status of the PLE channels.

Processes that handle PLE can read this register to determine the physical resources implemented and their availability.

The PLE Identification and Status Register is:

  • four read-only registers common to Secure and Nonsecure states

  • accessible only in privileged modes.

Figure 3.53 shows the bit arrangement of the PLE Identification and Status Registers 0-3.

Figure 3.53. PLE identification and Status Registers format

Figure 3.53. PLE identification and Status Registers
format

Table 3.118 shows how the bit values correspond with the PLE Identification and Status Registers functions.

Table 3.118. PLE Identification and Status Register bit functions

Bits

Field

Function
[31:2]-

Reserved. UNP, SBZ.

[1]CH1

Provides information on PLE Channel 1 functions:

0 = PLE Channel 1 function disabled

1 = PLE Channel 1 function enabled. This is the reset value.

[0]CH0

Provides information on PLE Channel 0 functions:

0 = PLE Channel 0 function disabled

1 = PLE Channel 0 function enabled. This is the reset value.


Table 3.119 shows the Opcode_2 values for PLE channel function selection.

Table 3.119. Opcode_2 values for PLE Identification and Status Register functions
Opcode_2Function
0

Indicates channel present:

0 = channel is not present

1 = channel is present.

1

Reserved. Does not result in an Undefined Instruction exception.

2

Indicates channel running:

0 = channel is not running

1 = channel is running.

3

Indicates channel interrupting:

0 = channel is not interrupting

1 = channel is interrupting, through completion or an error.

4-7

Reserved. Results in an Undefined Instruction exception.


Access in the Nonsecure state depends on the PLE bit, see c1, Nonsecure Access Control Register. The processor can only access these registers in privileged modes. Table 3.120 shows the results of attempted access for each mode.

Table 3.120. Results of access to the PLE Identification and Status Registers[48]
 Secure privilegedNonsecure privilegedSecure UserNonsecure User

PLE

bit

ReadWriteReadWriteReadWriteReadWrite
0DataUndefinedUndefinedUndefinedUndefinedUndefinedUndefinedUndefined
1DataUndefinedDataUndefinedUndefinedUndefinedUndefinedUndefined

[48] An entry of Undefined in the table means that the access gives an Undefined Instruction exception when the coprocessor instruction is executed.


To access the PLE Identification and Status Registers in a privileged mode, read CP15 with:

            MRC p15, 0, <Rd>, c11, c0, 0 ; Read PLE Identification and Status Register present
            MRC p15, 0, <Rd>, c11, c0, 2 ; Read PLE Identification and Status Register running
            MRC p15, 0, <Rd>, c11, c0, 3 ; Read PLE Identification and Status Register interrupting