The purpose of the PLE User Accessibility Register is to determine if a User mode process can access the registers for each channel. This register contains a bit for each channel, referred to as the U bit for that channel.
The PLE User Accessibility Register is:
a read/write register common to the Secure and Nonsecure states
accessible in privileged modes only.
Figure 3.54 shows the bit arrangement of the PLE User Accessibility Register.
Table 3.121 shows how the bit values correspond with the PLE User Accessibility Register functions.
Reserved. UNP, SBZP.
Indicates if a User mode process can access the registers for channel 1:
0 = User mode cannot access channel 1, reset value. User mode accesses cause an Undefined Instruction exception.
1 = User mode can access channel 1.
Indicates if a User mode process can access the registers for channel 0:
0 = User mode cannot access channel 0, reset value. User mode accesses cause an Undefined Instruction exception.
1 = User mode can access channel 0.
Access in the Nonsecure state depends on the PLE bit, see c1, Nonsecure Access Control Register. The processor can only access this register in privileged modes. Table 3.122 shows the results of attempted access for each mode.
|Secure privileged||Nonsecure privileged||Secure User||Nonsecure User|
 An entry of Undefined in the table means that the access gives an Undefined Instruction exception when the coprocessor instruction is executed.
To access the PLE User Accessibility Register, read or write CP15 with:
MRC p15, 0, <Rd>, c11, c1, 0 ; Read PLE User Accessibility Register
MCR p15, 0, <Rd>, c11, c1, 0 ; Write PLE User Accessibility Register
The registers that you can access in User mode when the U1 or U0 bit = 1 for the current channel are:
You can access the PLE Channel Number Register, see c11, PLE Channel Number Register, in User mode when the U1 or U0 bit for any channel is 1.
The contents of these registers must be preserved on a task switch if the registers are user accessible.
If the U bit for the currently selected channel is set to 0, and a User mode process attempts to access any of these registers, the processor takes an Undefined instruction trap.