The purpose of the Translation Table Base Register 0 is to hold the physical address of the first level translation table.
You use Translation Table Base Register 0 for process-specific addresses, where each process maintains a separate first level translation table. On a context switch you must modify both Translation Table Base Register 0 and the Translation Table Base Control Register, if appropriate.
The Translation Table Base Register 0 is:
a read/write register banked for Secure and Nonsecure states
accessible in privileged modes only.
Figure 3.26 shows the bit arrangement of the Translation Table Base Register 0.
Table 3.60 shows how the bit values correspond with the Translation Table Base Register 0 functions.
|[31:14-N]||Translation table base 0||Holds the translation table base address, the physical address of the first level translation table.|
|[13-N:5]a||-||Reserved. RAZ, SBZ.|
Indicates the outer cacheable attributes for translation table walking:
b00 = outer noncacheable
b01 = write-back, write allocate
b10 = write-through, no allocate on write
b11 = write-back, no allocate on write.
|||P||Read-As-Zero and ignore writes. This bit is not implemented on this processor.|
Indicates the translation table walk is to nonshared or to shared memory:
0 = nonshared
1 = shared.
Indicates the translation table walk is inner cacheable or inner noncacheable:
0 = inner noncacheable
1 = inner cacheable.
Attempts to write to this register in secure privileged mode when CP15SDISABLE is HIGH result in an Undefined Instruction exception, see Security Extensions write access disable.
Table 3.61 shows the results of attempted access for each mode.
|Secure privileged||Nonsecure privileged||Secure User||Nonsecure User|
|Secure data||Secure data||Nonsecure data||Nonsecure data||Undefined||Undefined||Undefined||Undefined|
 An entry of Undefined in the table means that the access gives an Undefined Instruction exception when the coprocessor instruction is executed.
A write to the Translation Table Base Register 0 updates the address of the first level translation table from the value in bits [31:7] of the written value, to account for the maximum value of 7 for N. The number of bits of this address that the processor uses, and the required alignment of the first level translation table, depends on the value of N, see c2, Translation Table Base Control Register.
A read from the Translation Table Base Register 0 returns the complete address of the first level translation table in bits [31:7] of the read value, regardless of the value of N.
To access the Translation Table Base Register 0, read or write CP15 c2 with:
MRC p15, 0, <Rd>, c2, c0, 0 ; Read Translation Table Base Register
MCR p15, 0, <Rd>, c2, c0, 0 ; Write Translation Table Base Register
The processor cannot perform a translation table walk from L1 cache. Therefore, if C is set to 1, to ensure coherency, you must store translation tables in inner write-through memory. If you store the translation tables in an inner write-back memory region, you must clean the appropriate cache entries after modification so that the mechanism for the hardware translation table walks sees them.