The purpose of the TLB operations is to either:
invalidate all the unlocked entries in the TLB
invalidate all TLB entries for an area of memory before the MMU remaps it
invalidate all TLB entries that match an ASID value.
You can perform these operations on either:
To perform TLB operations, write CP15 with:
MCR p15, 0, <Rd>, c8, c5, 0 ; Invalidate Inst-TLB
MCR p15, 0, <Rd>, c8, c5, 1 ; Invalidate Inst-TLB entry (MVA)
MCR p15, 0, <Rd>, c8, c5, 2 ; Invalidate Inst-TLB (ASID)
MCR p15, 0, <Rd>, c8, c6, 0 ; Invalidate Data-TLB
MCR p15, 0, <Rd>, c8, c6, 1 ; Invalidate Data-TLB entry (MVA)
MCR p15, 0, <Rd>, c8, c6, 2 ; Invalidate Data-TLB (ASID)
MCR p15, 0, <Rd>, c8, c7, 0 ; Invalidate Inst-TLB and Data-TLB
MCR p15, 0, <Rd>, c8, c7, 1 ; Invalidate Inst-TLB and Data-TLB entry (MVA)
MCR p15, 0, <Rd>, c8, c7, 2 ; Invalidate Inst-TLB and Data-TLB (ASID)
All other ARMv7-A TLB maintenance encodings are Unpredictable.
Functions that update the contents of the TLB occur in program order. Therefore, an explicit data access before the TLB function uses the old TLB contents, and an explicit data access after the TLB function uses the new TLB contents. For instruction accesses, TLB updates are guaranteed to have taken effect before the next pipeline flush. This includes flush prefetch buffer operations and exception return sequences.
Invalidate TLB unlocked entries invalidates all the unlocked entries in the TLB.
For an area of memory to be remapped, you can use the Invalidate TLB Entry by MVA to invalidate any TLB entry, locked or unlocked, by either:
matching the MVA and ASID
matching the MVA for a globally marked TLB entry.
The operation uses both the MVA and ASID as arguments. Figure 3.36 shows the format.
This operation invalidates all TLB entries that match the provided ASID value. This function invalidates locked entries but does not invalidate entries marked as global.
The Invalidate TLB Entry on ASID Match function requires an ASID as an argument. Figure 3.37 shows the format.