The purpose of the CouNT ENable Clear (CNTENC) Register is to enable or disable any of the Performance Monitor Count Registers.
When reading this register, any enable that reads as 0 indicates the counter is disabled. Any enable that reads as 1 indicates the counter is enabled.
When writing this register, any enable written with a value of 0 is ignored, that is, not updated. Any enable written with a value of 1 clears the counter enable to 0.
The CNTENC Register is:
a read/write register common to Secure and Nonsecure states
accessible as determined by c9, User Enable Register.
Figure 3.40 shows the bit arrangement of the CNTENC Register.
Table 3.86 shows how the bit values correspond with the CNTENC Register functions.
Disable cycle counter.
Reserved. UNP, SBZP.
Disable Counter 3.
Disable Counter 2.
Disable Counter 1.
Disable Counter 0.
Table 3.87 shows the results of attempted access for each mode.
|EN = 0|
|EN = 1|
 The access gives an Undefined Instruction exception when the coprocessor instruction is executed.
To access the CNTENC Register, read or write CP15 with:
MRC p15, 0, <Rd>, c9, c12, 2 ; Read CNTENC Register
MCR p15, 0, <Rd>, c9, c12, 2 ; Write CNTENC Register
You can use the enable, EN, bit  of the PMNC Register to disable all performance counters including CCNT. The CNTENC Register retains its value when the enable bit of the PMNC is set to 0, even though its settings are ignored.