The purpose of the CouNT ENable Set (CNTENS) Register is to enable or disable any of the Performance Monitor Count Registers.
When reading this register, any enable that reads as 0 indicates the counter is disabled. Any enable that reads as 1 indicates the counter is enabled.
When writing this register, any enable written with a value of 0 is ignored, that is, not updated. Any enable written with a value of 1 indicates the counter is enabled.
The CNTENS Register is:
a read/write register common to Secure and Nonsecure states
accessible as determined by c9, User Enable Register.
Figure 3.39 shows the bit arrangement of the CNTENS Register.
Table 3.84 shows how the bit values correspond with the CNTENS Register functions.
Enable cycle counter.
Reserved. UNP, SBZ.
Enable Counter 3.
Enable Counter 2.
Enable Counter 1.
Enable Counter 0.
Table 3.85 shows the results of attempted access for each mode.
 An entry of Undefined in the table means that the access gives an Undefined Instruction exception when the coprocessor instruction is executed.
To access the CNTENS Register, read or write CP15 with:
MRC p15, 0, <Rd>, c9, c12, 1 ; Read CNTENS Register
MCR p15, 0, <Rd>, c9, c12, 1 ; Write CNTENS Register