The purpose of the INTerrupt ENable Clear (INTENC) Register is to determine if any of the Performance Monitor Count Registers, PMCNT0-PMCNT3 and CCNT, generate an interrupt on overflow.
The INTENC Register is:
a read/write register common to Secure and Nonsecure states
accessible in privileged mode only.
When reading this register, any interrupt overflow enable bit that reads as 0 indicates the interrupt overflow flag is disabled. Any interrupt overflow enable bit that reads as 1 indicates the interrupt overflow flag is enabled.
When writing this register, any interrupt overflow enable bit written with a value of 0 is ignored, that is, not updated. Any interrupt overflow enable bit written with a value of 1 clears the interrupt overflow enable bit to 0.
Figure 3.47 shows the bit arrangement of the INTENC Register.
Table 3.104 shows how the bit values correspond with the INTENC Register functions.
CCNT overflow interrupt enable.
|[30:4]||-||Reserved. UNP, SBZP.|
PMCNT3 overflow interrupt enable.
PMCNT2 overflow interrupt enable.
PMCNT1 overflow interrupt enable.
PMCNT0 overflow interrupt enable.
Table 3.105 shows the results of attempted access for each mode.
 An entry of Undefined in the table means that the access gives an Undefined Instruction exception when the coprocessor instruction is executed.
To access the INTENC Register, read or write CP15 with:
MRC p15, 0, <Rd>, c9, c14, 2 ; Read INTENC Register
MCR p15, 0, <Rd>, c9, c14, 2 ; Write INTENC Register