The purpose of the Overflow Flag Status (FLAG) Register is to enable or disable any of the performance monitor counters producing an overflow flag.
When reading this register, any overflow flag that reads as 0 indicates the counter has not overflowed. Any overflow flag that reads as 1 indicates the counter has overflowed.
When writing this register, any overflow flag written with a value of 0 is ignored, that is, not updated. Any overflow flag written with a value of 1 clears the counter overflow flag to 0.
The FLAG Register is:
a read/write register common to Secure and Nonsecure states
accessible as determined by c9, User Enable Register.
Figure 3.41 shows the bit arrangement of the FLAG Register.
Table 3.88 shows how the bit values correspond with the FLAG Register functions.
Cycle counter overflow flag.
Reserved. UNP, SBZP.
Counter 3 overflow flag.
Counter 2 overflow flag.
Counter 1 overflow flag.
Counter 0 overflow flag.
Table 3.89 shows the results of attempted access for each mode.
 An entry of Undefined in the table means that the access gives an Undefined Instruction exception when the coprocessor instruction is executed.
To access the FLAG Register, read or write CP15 with:
MRC p15, 0, <Rd>, c9, c12, 3 ; Read FLAG Register
MCR p15, 0, <Rd>, c9, c12, 3 ; Write FLAG Register