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Appendix C. Revisions

This appendix describes the technical changes between released issues of this book.

Table C.1. Differences between issue F and issue G
Added description of product documentation and architectureProduct documentation and architecture
Updated reset value of Main ID Register
Updated bit assignments and description of Auxiliary Control Registerc1, Auxiliary Control Register
Show effect of improved cache maintenanceTable 3.73
Changed description of values for predefined events 0x45 and 0x46Table 3.97
Expanded description of DT field in PLE Control RegisterTable 3.126
Updated description of L1 memory system
Added section on instruction cache maintenanceInstruction cache maintenance
Reorganized tables for AXI ID assignmentsAXI identifiers
Updated descriptions of AXI address channel for data transactionsTable 9.7
Added table showing number of transfers on AXI write channel for an evictionEvictions
Clarified timing diagram of STANDBYWFI deassertionFigure 10.9
Updated field values for Debug ID RegisterCP14 c0, Debug ID Register
Updated field values for Peripheral ID Register 2
Updated ID Register bit assignmentsFigure 14.2
Added tables to show the effect of CP15 cache maintenanceCoprocessor instructions
Added footnote to clarify back-to-back execution of certain multiply and multiply-accumulate instructionsTable 16.19
Added Note to clarify operation of Advanced SIMD floating-point instructionsAdvanced SIMD floating-point instructions
Expanded description of VFP instruction executionVFP instruction execution in the NFP pipeline

Table C.2. Differences between issue G and issue H
Amended function description for invalidate instruction cache lineTable 3.73

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