You copied the Doc URL to your clipboard.

15.7.1. ITTRIGINACK, 0xEE0

ITTRIGINACK is a write-only register. This register controls signal outputs when bit [0] of the Integration Mode Control Register is set to 1. Figure 15.17 shows the bit arrangement of the ITTRIGINACK Register.

Figure 15.17. ITTRIGINACK Register format

Figure 15.17. ITTRIGINACK Register format

Table 15.18 shows how the bit values correspond with the ITTRIGINACK Register functions.

Table 15.18. ITTRIGINACK Register bit functions
[31:9] -Reserved, SBZ
[8:0]CTTRIGINACKSets the value of the CTTRIGINACK outputs

Each bit of the ITTRIGINACK Register corresponds to a bit on the ITTRIGIN Register. When in integration mode and a trigger input is cleared, you must set the appropriate bit in the ITTRIGINACK Register to 1, to enable the previous trigger input condition to be acknowledged and cleared. If you do not set the appropriate bit in ITTRIGINACK, the CTI synchronization logic causes the trigger input to continue to be asserted.

No bits of the ITTRIGINACK Register are connected to other integration test registers in the processor.