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15.6.12. ASIC Control Register, ASICCTL

The ASICCTL Register is a read/write register that controls edge detection on trigger outputs. Figure 15.15 shows the bit assignments of the ASIC Control Register.

Figure 15.15. ASIC Control Register format

Figure 15.15. ASIC Control Register format

Table 15.15 shows how the bit values correspond with the ASIC Control Register functions.

Table 15.15. ASIC Control Register bit functions
BitsFieldFunction

[31:6]

-

Reserved. RAZ, SBZ.

[5]

PMUEXTIN1EDGE

Enables edge detection for trigger output 6, PMU CTI event 1.

[4]

PMUEXTIN0EDGE

Enables edge detection for trigger output 5, PMU CTI event 0.

[3]

ETMEXTIN4EDGE

Enables edge detection for trigger output 4, ETM external input 4.

[2]

ETMEXTIN3EDGE

Enables edge detection for trigger output 3, ETM external input 3.

[1]

ETMEXTIN2EDGE

Enables edge detection for trigger output 2, ETM external input 2.

[0]

ETMEXTIN1EDGE

Enables edge detection for trigger output 1, ETM external input 1.


You can enable edge detection for each trigger output that is used in the CLK domain. If edge detection is enabled:

  • a single PMU CTI event is generated for every rising edge of the trigger output

  • the ETM external input is HIGH for one CLK cycle for every rising edge of the trigger output.