These registers are read/write registers that enable the signalling of an event on a CTM channel or CTM channels when the core issues a CTITRIGIN trigger input to the CTI. There is one register for each of the nine trigger inputs. Only seven trigger inputs are used, so CTIINEN7 and CTIINEN8 are present but not used. Within each register there is one bit for each of the four channels implemented. These registers do not affect the application trigger operations.
Figure 15.9 shows the bit arrangement of these registers.
Table 15.9 shows how the bit values correspond with these registers.
Reserved. RAZ, SBZ.
Enables a cross trigger event to the corresponding channel when CTITRIGIN is activated:
0 = disables the CTITRIGIN signal from generating an event on the respective channel of the CTM
1 = enables the CTITRIGIN signal to generate an event on the respective channel of the CTM.
There is one bit of the register for each of the four channels. For example, TRIGINEN set to 1 in Register CTIINEN0, enables CTITRIGIN onto channel 0.