The Debug Self Address Offset Register is a read-only register that returns a 20-bit offset value from the Debug ROM Address Register to the physical address of the processor debug registers. The address read from this register depends on the DBGSELFADDR[31:12] and DBGSELFADDRV inputs. DBGSELFADDRV must be tied off to 1 if DBGSELFADDR[31:12] is tied off to a valid value.
The Debug Self Address Offset Register is:
in CP14 c0
a read-only register
accessible in User and privileged modes.
Figure 12.4 shows the bit arrangement of the Debug Self Address Offset Register.
Table 12.13 shows how the bit values correspond with the Debug Self Address Offset Register functions.
|Debug bus self-address offset value|
Indicates bits [31:12] of the 2’s complement offset from the debug ROM physical address to the physical address of the start of the region where the debug registers are mapped. The value read by this field corresponds to the value of DBGSELFADDR[31:12].
Reserved. RAZ, SBZP.
Reads b11 if DBGSELFADDRV is set to 1, reads b00 otherwise. DBGSELFADDRV must be set to 1 if DBGSELFADDR[31:12] is set to a valid value.
To access the Debug Self Address Offset Register, read CP14 c0 with:
MRC p14, 0, <Rd>, c2, c0, 0 ; Read Debug Self Address Offset Register