The DSCCR controls both L1 and L2 cache behavior while the processor is in debug state.
Figure 12.9 shows the bit arrangement of the DSCCR.
See Cache debug for information on the usage model of the DSCCR register.
Table 12.19 shows how the bit values correspond with the Debug State Cache Control Register functions.
|Reserved. RAZ, SBZP.|
0 = force write-through behavior for regions marked as write-back in debug state, reset value
1 = normal operation of regions marked as write-back in debug state.
Reserved. RAZ, SBZP.
|Data and unified cache linefill|
Data and unified cache linefill:
0 = L1 data cache and L2 cache linefills disabled in debug state, reset value
1 = normal operation of L1 data cache and L2 cache in debug state.