The ECR enables the external debugger or debug monitor to configure the debug logic to trigger a debug state or debug exception entry on certain events.
Figure 12.8 shows the bit arrangement of the ECR.
Table 12.18 shows how the bit values correspond with the Event Catch Register functions.
|[31:1]||-||Reserved. RAZ, SBZP.|
|||OS unlock catch|
OS unlock catch:
0 = catch disabled, reset value
1 = catch enabled.
When this bit is set to 1, the debug logic generates a debug event when the OS lock state transitions from 1 to 0. This debug event might trigger a debug state entry, or might be ignored, depending on the invasive debug security configuration. The OS unlock catch debug event is a halting debug event and, therefore it cannot cause a debug exception.
If you are debugging an application running on top of an OS that preserves the state of the debug unit when powering down the core, this event indicates when the debug session can continue.