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12.4.11. Instruction Transfer Register

The ITR enables the external debugger to feed instructions into the core for execution while in debug state. The ITR is a write-only register. Reads from the ITR return an Unpredictable value.

Figure 12.10 shows the bit arrangement of the ITR.

Figure 12.10. ITR format

Figure 12.10. ITR format

Table 12.20 shows how the bit values correspond with the Instruction Transfer Register functions.

Table 12.20. Instruction Transfer Register bit functions



Indicates an ARM instruction for the processor to execute while in debug state. The reset value is Unpredictable.


Writes to the ITR when the processor is not in debug state or the DSCR[13] execute instruction enable bit is 0 are Unpredictable.