The Cortex-A8 core has separate safe shift RAM signal for each logical unit that uses it, they are:
These safe shift RAM signals are top-level signals with scan enable functionality. They are asserted during scan shifting to gate off the chip selects and write enables of the L1 cache RAMs. These signals are also used to gate off the clock signal to the L2 cache RAMs, as Figure 11.30 shows.
One methodology for testing the shadow logic of the RAMs is to test through the RAMs. The ATPG tool uses this gate for easier testability of this logic for this methodology. However, if there is a scan chain or bypass wrapper within the RAM, this gate prevents the clock from toggling during shift and causes the chain or wrapper to be ignored during test. If you do not require this gate, you can optimize it out during synthesis by setting SAFESHIFTRAMIF, SAFESHIFTRAMLS, or SAFESHIFTRAML2 LOW.
When removing the safe shift RAM gate from a logical unit, all RAMs in that logical unit are affected.