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8.7. Parity and error correction code

The L2 memory supports parity detection on the tag arrays. The data arrays can support parity or Error Correction Code (ECC). If ECC support is implemented, two extra cycles are added to the L2 pipeline to perform the checking and correction functionality. In addition, ECC introduces extra cycles to support read-modified-write conditions when a subset of the data covered by the ECC logic is updated. The ECC supports single-bit correction and double-bit detection.

The L2 Cache Auxiliary Control Register bits [28] and [21] control the parity and ECC support.

If a cache access result is a parity error or double bit ECC error in the L2 Cache, then both the L1 data cache and the L2 cache are unpredictable. No recovery is possible. The abort handler must:

  • disable the caches

  • communicate the fail directly with the external system

  • request a reboot.

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