The processor supports supersections that consist of 16MB blocks of memory. The processor does not support the optional extension of physical address bits [39:32].
Figure 6.1 shows the descriptor format for supersections.
Each translation table entry for a supersection must be repeated 16 times in consecutive memory locations in the level 1 translation tables, and each of the 16 repeated entries must have identical translation and permission information. See the ARM Architecture Reference Manual for more information.