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3.2.27. c1, Coprocessor Access Control Register

The purpose of the Coprocessor Access Control Register is to set access rights for the coprocessors CP0 through CP13. This register has no effect on access to CP14, the debug control coprocessor, or CP15, the system control coprocessor. This register also provides a means for software to determine if any particular coprocessor, CP0-CP13, exists in the system.

The Coprocessor Access Control Register is:

  • a read/write register common to Secure and Nonsecure states

  • accessible in privileged modes only.

Figure 3.22 shows the bit arrangement of the Coprocessor Access Control Register.

Figure 3.22. Coprocessor Access Control Register format

Figure 3.22. Coprocessor Access Control Register

Table 3.51 shows how the bit values correspond with the Coprocessor Access Control Register functions.

Table 3.51. Coprocessor Access Control Register bit functions
[31:28]-Reserved. UNP, SBZP.

Defines access permissions for each coprocessor. Access denied is the reset condition and is the behavior for nonexistent coprocessors:

b00 = Access denied, reset value. Attempted access generates an Undefined Instruction exception.

b01 = Privileged mode access only.

b10 = Reserved.

b11 = Privileged and User mode access.

[1] n is the coprocessor number between 0 and 13.

Access to coprocessors in the Nonsecure state depends on the permissions set in the c1, Nonsecure Access Control Register.

Attempts to read or write the Coprocessor Access Control Register access bits depend on the corresponding bit for each coprocessor in c1, Nonsecure Access Control Register. Table 3.52 shows the results of attempted access to coprocessor access bits for each mode.

Table 3.52. Results of access to the Coprocessor Access Control Register[25]
 Secure privilegedNonsecure privilegedSecure UserNonsecure User


Access Control

Register bit


[25] An entry of Undefined in the table means that the access gives an Undefined Instruction exception when the coprocessor instruction is executed.

To access the Coprocessor Access Control Register, read or write CP15 with:

MRC p15, 0, <Rd>, c1, c0, 2 ; Read Coprocessor Access Control Register
MCR p15, 0, <Rd>, c1, c0, 2 ; Write Coprocessor Access Control Register

You must execute an Instruction Memory Barrier (IMB) sequence immediately after an update of the Coprocessor Access Control Register, see Memory Barriers in the ARM Architecture Reference Manual. You must not attempt to execute any instructions that are affected by the change of access rights between the IMB sequence and the register update.

To determine if any particular coprocessor exists in the system, write the access bits for the coprocessor of interest with a value other than b00. If the coprocessor does not exist in the system the access rights remain set to b00.


  • For the processor, there is a direct relationship between the CPEXIST[13:0] inputs and the Coprocessor Access Control Register bits cp13-cp01.

    Each CPEXIST input represents the existence of a coprocessor that you use to enable a particular coprocessor. If the appropriate CPEXIST input is set to a:

    • logical 0, access is denied to that coprocessor or reset state as defined by the register

    • logical 1, then you can reprogram that coprocessor.

  • You must enable the Coprocessor Access Control Register before accessing any NEON or VFP system register.

  • You must set CPEXIST[11:10] to b11 to use the NEON or VFP coprocessor. All other CPEXIST bits must be set to 0.

  • You must set CPEXIST[11:10] to b00 if you configure the processor without the NEON coprocessor.

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