The purpose of the PLE Control Register for each channel is to control the operations of that PLE channel.
Table 3.126 shows the purposes of the individual bits in the PLE Control Register.
The PLE Control Register is:
one read/write register for each PLE channel common to Secure and Nonsecure states
accessible in User and privileged modes.
Figure 3.56 shows the bit arrangement of the PLE Control Register.
Table 3.126 shows how the bit values correspond with the PLE Control Register functions.
|||-||Reserved. UNP, SBZP.|
Indicates direction of transfer:
0 = transfer from AXI SoC memory to the L2 cache, performing cache linefill.
1 = transfer from L2 cache to AXI SoC memory, performing a cache clean-and-invalidate operation.
Indicates whether the PLE channel must assert an interrupt on completion of the PLE transfer, or if the Stop command stops the PLE, see c11, PLE enable commands.
The interrupt is deasserted from this source, if the processor performs a clear operation on the channel that caused the interrupt. See c11, PLE enable commands for more information.
The U bit has no affect on whether an interrupt is generated on completion.
0 = no interrupt on completion
1 = interrupt on completion.
Indicates that the PLE channel must assert an interrupt on an error.
The interrupt is deasserted from this source, when the channel is set to idle with a clear operation. See c11, PLE enable commands for more information.
If the U bit is set to 1, then an interrupt on error occurs regardless of the state of the IE bit. See c11, PLE User Accessibility Register for information on the U bit.
0 = no interrupt on error
1 = interrupt on error.
Reserved. UNP, SBZP.
Indicates that the permission checks are based on the PLE in User or privileged mode. The UM bit is provided so that the privileged mode process can emulate a User mode. See Table 3.127 for more details on the UM bit:
0 = transfer is a privileged transfer
1 = transfer is a User mode transfer.
Reserved. UNP, SBZP.
Indicates the selected L2 cache way for filling data. This is used in conjunction with the L2 Cache Lockdown Register:
b000 = way 0
b001 = way 1
b010 = way 2
b011 = way 3
b100 = way 4
b101 = way 5
b110 = way 6
b111 = way 7.
Access in the Nonsecure state depends on the PLE bit, see c1, Nonsecure Access Control Register. The processor can access this register in User mode if the U bit for the currently selected channel is set to 1, see c11, PLE User Accessibility Register.
Table 3.127 shows the behavior of the processor when writing the UM bit  for various processor modes and U bit settings.
|Data to be written to UM bit ||Mode of CP15 instruction||User accessibility (U bit)||Value written to UM bit |
|b1||User mode||b0||Undefined Instruction exception taken|
|b0||User mode||b0||Undefined Instruction exception taken|
Table 3.128 shows the results of attempted access for each mode.
|Secure privileged||Nonsecure privileged||Secure User||Nonsecure User|
|U bit||PLE bit||Read||Write||Read||Write||Read||Write||Read||Write|
 An entry of Undefined in the table means that the access gives an Undefined Instruction exception when the coprocessor instruction is executed.
To access the PLE Control Register, set the PLE Channel Number Register to the appropriate PLE channel and read or write CP15 with:
MRC p15, 0, <Rd>, c11, c4, 0 ; Read PLE Control Register
MCR p15, 0, <Rd>, c11, c4, 0 ; Write PLE Control Register
While the channel has the status of Running, any attempt to write to the PLE Control Register results in architecturally Unpredictable behavior. For the processor, writes to the PLE Control Register have no effect when the PLE channel is running.