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4.2. Unaligned data access support

The processor supports loads and stores of unaligned words and halfwords. The processor makes the required number of memory accesses and transfers adjacent bytes transparently.

Note

Data accesses that cross a word boundary can add to the access time.

Setting the A bit in the CP15 c1 Control Register enables alignment checking. When the A bit is set to 1, two types of memory access generate a Data Abort signal and an Alignment fault status code:

  • a 16-bit access that is not halfword-aligned

  • a 32-bit load or store that is not word-aligned.

Alignment fault detection is a mandatory address-generation function rather than an optionally supported function of external memory management hardware.

See the ARM Architecture Reference Manual for more information on unaligned data access support.

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