The instruction decode unit decodes and sequences all ARM and Thumb-2 instructions including debug control coprocessor, CP14, instructions and system control coprocessor, CP15, instructions. See Chapter 12 Debug for information on the CP14 coprocessor and Chapter 3 System Control Coprocessor for information on the CP15 coprocessor.
The instruction decode unit handles the sequencing of:
Memory Built-In Self Test (MBIST)
other unusual events.
See Chapter 16 Instruction Cycle Timing for more information on how the processor sequences instructions.