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1.3.2. Instruction decode

The instruction decode unit decodes and sequences all ARM and Thumb-2 instructions including debug control coprocessor, CP14, instructions and system control coprocessor, CP15, instructions. See Chapter 12 Debug for information on the CP14 coprocessor and Chapter 3 System Control Coprocessor for information on the CP15 coprocessor.

The instruction decode unit handles the sequencing of:

  • exceptions

  • debug events

  • reset initialization

  • Memory Built-In Self Test (MBIST)

  • wait-for-interrupt

  • other unusual events.

See Chapter 16 Instruction Cycle Timing for more information on how the processor sequences instructions.

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