The instruction execute unit consists of two symmetric Arithmetic Logical Unit (ALU) pipelines, an address generator for load and store instructions, and the multiply pipeline. The execute pipelines also perform register write back.
The instruction execute unit:
executes all integer ALU and multiply operations including flag generation
generates the virtual addresses for loads and stores and the base write-back value, when required
supplies formatted data for stores and also forwards data and flags
processes branches and other changes of instruction stream and evaluates instruction condition codes.