The load/store unit encompasses the entire L1 data side memory system and the integer load/store pipeline. This includes:
the L1 data cache
the data side TLB
the integer store buffer
the NEON store buffer
the integer load data alignment and formatting
the integer store data alignment and formatting.
The pipeline accepts one load or store per cycle that can be present in either pipeline 0 or pipeline 1. This gives the processor flexibility when scheduling load and store instructions. See Chapter 7 Level 1 Memory System for more information.