Each cache is 4-way set associative of configurable size. They are physically tagged, and virtually indexed for instruction and physically indexed for data. The cache sizes are configurable with sizes of 16KB or 32KB. Both the instruction cache and the data cache are capable of providing two words per cycle for all requesting sources. Data cache can provide four words per cycle for NEON or VFP memory accesses.
The system control coprocessor, CP15, handles the control of the L1 memory system and the associated functionality, together with other system wide control attributes. See Chapter 3 System Control Coprocessor for more information on CP15 registers.