On previous versions of the ARM architectures, support for
shared memory synchronization was with the read-locked-write operations
that swap register contents with memory, the
These support basic busy and free semaphore mechanisms. See the ARM
Architecture Reference Manual for details of the swap
ARMv7-A describes support for more comprehensive shared-memory synchronization primitives that scale for multiple-processor system designs. Two sets of instructions are introduced to support multiple-processor and shared-memory inter-process communication:
The exclusive-access instructions rely on the ability to tag a physical address as exclusive-access for a particular processor. This tag is later used to determine if an exclusive store to an address occurs.
For nonshared memory regions, the
are presented to the ports as normal
If a processor does an
STR on a memory region that
it has already marked as exclusive, this does not clear the tag.
However, if the region has been marked by another processor, an
Other events might cause the tag to be cleared. In particular, for memory regions that are not shared, it is Unpredictable whether a store by another processor to a tagged physical address causes the tag to be cleared.
An external abort on either a load-exclusive or store-exclusive puts the processor into Abort mode.
An external abort on a load-exclusive can leave the processor
internal monitor in its exclusive state and might affect your software.
If it does, you must execute a store-exclusive to an unused location
in your abort handler or use the
CLREX instruction to
clear the processor internal monitor to an open state.