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A.3.1. MBIST interface

Table A.3 shows the MBIST interface signals. All MBIST interface signals are registered. All MBIST signals from Table A.3 must be controllable from external SoC pins for use by ATE.

Table A.3. MBIST interface
SignalI/OResetDescription
MBISTDATAINL1I-Serial data input for loading the L1 MBIST Instruction Register
MBISTDSHIFTL1I-Enables download of the L1 MBIST Datalog Register on MBISTRESULTL1[0] when MBISTSHIFTL1 is set to 0.
MBISTRUNL1I-Enables execution of the loaded L1 MBIST instruction.
MBISTSHIFTL1I-Enables serial loading of the L1 MBIST Instruction Register when MBISTDSHIFTL1 is set to 0 or enables serial loading of the L1 MBIST GO-NOGO Instruction Register when MBISTDSHIFTL1 is set to 1.
MBISTRESULTL1[2:0]OUndefined

L1 MBIST controller status and data output:

MBISTRESULTL1[0] = address expire flag or L1 MBIST Datalog Register output

MBISTRESULTL1[1] = fail flag

MBISTRESULTL1[2] = test complete flag.

MBISTDATAINL2I-Serial data input for loading the L2 MBIST Instruction Register.
MBISTDSHIFTL2I-Enables download of the L2 MBIST Datalog Register on MBISTRESULTL2[0].
MBISTRUNL2I-Enables execution of the loaded L2 MBIST instruction.
MBISTSHIFTL2I-Enables serial loading of the L2 MBIST Instruction Register.
MBISTRESULTL2[2:0]OUndefined

L2 MBIST controller status and data output:

MBISTRESULTL2[0] = address expire flag or L2 MBIST Datalog Register output

MBISTRESULTL2[1] = fail flag

MBISTRESULTL2[2] = test complete flag.

MBISTUSERINL2[18:0]I-L2 MBIST configuration pins reserved for future expansion. Tie these pins LOW.
MBISTUSEROUTL2[4:0]OUndefinedL2 MBIST configuration pins reserved for future expansion. Ignore these pins.
CLKI-Clock input.
ARESETnI-Reset input[a].
nPORESETI-Reset input[a].

[a] Reset input is controlled in the same way during MBIST mode as during functional mode. See Reset domains for information on reset.