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17.7. DFT interface

Table 17.7 shows the setup and hold times for the DFT interface.

Table 17.7. Timing parameters of the DFT interface
SignalClockSetup parameterPercent of clock period Hold parameter
SECLKTisse30%Tihse
SERIALTESTCLKTisserialtest30%Tihserialtest
SHIFTWRCLKTisshiftwr30%Tihshiftwr
CAPTUREWRCLKTiscapturewr30%Tihcapturewr
TESTMODECLKTistestmode30%Tihtestmode
TESTCGATECLKTistestcgate30%Tihtestcgate
TESTEGATECLKTistestegate30%Tihtestegate
TESTNGATECLKTistestngate30%Tihtestngate
WSECLKTiswse30%Tihwse
WEXTESTCLKTiswextest30%Tihwextest
WINTESTCLKTiswintest30%Tihwintest

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