During any transition of the power supply to a component of the processor, the asynchronous reset to that component must be asserted. This is a safety mechanism for implementation to ensure that hardware can be protected against supply transition, DC paths, such as precharge or discharge circuits, or bus contention. The primary inputs to the processor that act as asynchronous resets are:
If an implementation retains state in the L1 data cache or L2 cache as described, care must be taken that reset, particularly nPORESET, does not corrupt the state of the RAM arrays when lowering or raising the power supply to the rest of the processor. You can achieve this by clamping the primary I/O to the RAM arrays or designing the RAM arrays in such a way that they do not require a reset. If a reset is required, hardware must ensure that reset is inactive to those RAMs while clamped.