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10.2.1. Power-on reset

The power-on reset sequence is the most critical to the device because logic in all clock domains must be placed in a benign state following the deassertion of the reset sequence. Figure 10.5 shows the power-on reset sequence.

Figure 10.5. Power-on reset timing

Figure 10.5. Power-on reset timing

Figure 10.5 shows three critical aspects:

  1. At the beginning of power-on reset, CLK must be held LOW for a minimum of the equivalent of two REFCLK clock cycles to place components within the processor in a safe state.

  2. The nPORESET, PRESETn, and ATRESETn resets must be held for eight CLK cycles. This ensures that reset has propagated to all locations within the processor.

  3. The ARESETn and ARESETNEONn resets must be held for an additional eight CLK cycles following the release of nPORESET and PRESETn to enable those domains to exit reset safely.


  • The PCLK and ATCLK domains must also be reset during a power-on reset sequence to ensure that the interfaces between those domains and the CLK domain are reset properly.

    PRESETn and ATRESETn must be deasserted simultaneously with or after the deassertion of nPORESET.

  • Figure 10.5 shows that PRESETn must be asserted for a minimum of eight cycles. Because PCLK is an asynchronous clock domain that can operate faster or slower than CLK, PRESETn must be asserted for the slowest of eight CLK or eight PCLK cycles.

The power-on reset also controls entry and exit from a power-down state for various power domains within the processor. See Power control for more information.

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