The debugger or the system can cause the core to enter into debug state by triggering any of the following halting debug events:
assertion of the external debug request signal, EDBGRQ
write to the DRCR Halt Request control bit
detection of the OS unlock catch event
assertion of the Cross Trigger Interface debug request signal.
If EDBGRQ or CTI debug request is asserted while DBGEN is HIGH but invasive debug is not permitted, the devices that assert these signals must hold them until the processor enters debug state, that is, until DBGACK is asserted. Otherwise, the behavior of the processor is Unpredictable. For DRCR and OS unlock catch halting debug events, the processor records them internally until it is in a state and mode where they can be acknowledged.