You copied the Doc URL to your clipboard.

12.6.1. Software debug event

A software debug event is any of the following:

  • A watchpoint debug event. This occurs when:

    • The D-side Virtual Address (DVA) for a load or store matches the watchpoint value. Memory hints and cache operations do not trigger watchpoints.

    • All the conditions of the WCR match.

    • The watchpoint is enabled.

    • The linked context ID-holding BRP, if any, is enabled and its value matches the context ID in CP15 c13. See Chapter 3 System Control Coprocessor.

    • The instruction that initiated the memory access is committed for execution. Watchpoint debug events are only generated if the instruction passes its condition code.

  • A breakpoint debug event. This occurs when:

    • An instruction is fetched and the I-side Virtual Address (IVA) present in the instruction bus matched the breakpoint value.

    • At the same time the instruction is fetched, all the conditions of the BCR for linked or unlinked IVA-based breakpoint generation matched the I-side control signals.

    • The breakpoint is enabled.

    • At the same time the instruction is fetched, the linked context ID-holding BRP, if any, is enabled and its value matched the context ID in CP15 c13.

    • The instruction is committed for execution. These debug events are generated whether the instruction passes or fails its condition code.

  • A breakpoint debug event also occurs when:

    • An instruction is fetched and the CP15 Context ID Register c13 matched the breakpoint value.

    • At the same time the instruction is fetched, all the conditions of the BCR for unlinked context ID breakpoint generation matched the I-side control signals.

    • The breakpoint is enabled.

    • The instruction is committed for execution. These debug events are generated whether the instruction passes or fails its condition code.

  • A BKPT debug event. This occurs when a BKPT instruction is committed for execution. BKPT is an unconditional instruction.

  • A vector catch debug event. This occurs when:

    • An instruction is prefetched and the IVA matched a vector location address. This includes any kind of prefetches, not only the ones because of exception entry.

    • At the same time the instruction is fetched, the corresponding bit of the VCR is set to 1, that is, vector catch enabled.

    • Either the vector is not one of the Prefetch Abort or Data Abort vectors, or Halting debug mode is enabled.

    • The instruction is committed for execution. These debug events are generated whether the instruction passes or fails its condition code.