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12.5.5. Integration Mode Control Register

The read/write Integration Mode Control Register enables the processor to switch from a functional mode which is the default, into integration mode, where the inputs and outputs of the device can be directly controlled for integration testing or topology detection. When the processor is in this mode, you can use the Integration Internal Output Control Register or the Integration External Output Control Register to drive output values. You can use the Integration Input Status Register to read input values.

Figure 12.22 shows the bit arrangement of the Integration Mode Control Register.

Figure 12.22. Integration Mode Control Register format

Figure 12.22. Integration Mode Control Register

Table 12.37 shows how the bit values correspond with the Integration Mode Control Register functions.

Table 12.37. Integration Mode Control Register bit functions



Reserved. RAZ, SBZP.


Integration mode enable

Integration mode enable bit:

0 = normal operation, reset value

1 = integration mode enabled.

When this bit is set to 1, the processor reverts into integration mode to enable integration testing or topology detection.