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9.1. About the external memory interface

The external memory interface enables the processor to interface with third level caches, peripherals, and external memory. You can configure the processor to connect to either a 64-bit or 128-bit AXI interconnect that provides flexibility to system designs. The external memory interface supports the following interfaces:

  • read address channel

  • read data/response channel

  • write address channel

  • write data channel

  • write response channel.

All internal requests that require access to an external interface must use the appropriate external interface. You can generate requests with the following:

  • instruction fetch unit

  • load/store unit

  • table walk

  • preload engine

  • internal L2 cache controller.

By using the features of the AXI interconnect that enable split address and data transactions, in addition to multiple outstanding requests, the processor can reduce the external pin interface without reducing performance. The processor has a single AXI master interface. It does not contain an AXI slave interface.