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16.3. Dual-instruction issue restrictions

Calculating likely instruction pairings is part of the hand calculation process required to determine the timing for a sequence of instructions. The processor issues a pair of instructions unless it encounters an issue restriction. Table 16.15 shows the most common issue restriction cases. This table contains references to pipeline 0 and pipeline 1. The first instruction always issues in pipeline 0 and the second instruction, if present, issues in pipeline 1. If only one instruction issues, it always issues in pipeline 0.

Table 16.15. Dual-issue restrictions

Restriction

type

DescriptionExampleCycleRestriction

Load/store resource hazard

There is only one LS pipeline. Only one LS instruction can be issued per cycle. It can be in pipeline 0 or pipeline 1

LDR r5, [r6]

1-

STR r7, [r8]

2

Wait for LS unit

MOV r9, r10

2

Dual issue possible

Multiply resource hazard

There is only one multiply pipeline, and it is only available in pipeline 0.

ADD r1, r2, r3

1-

MUL r4, r5, r6

2

Wait for pipeline 0

MUL r7, r8, r9

3

Wait for multiply unit

Branch resource hazard

There can be only one branch per cycle. It can be in pipeline 0 or pipeline 1. A branch is any instruction that changes the PC.

BX r1

1-

BEQ 0x1000

2

Wait for branch

ADD r1, r2, r3

2

Dual issue possible

Data output hazard

Instructions with the same destination cannot be issued in the same cycle. This can happen with conditional code.

MOVEQ r1, r2

1-

MOVNE r1, r3

2

Wait because of output dependency

LDR r5, [r6]

2

Dual issue possible

Data source hazard

Instructions cannot be issued if their data is not available. See the scheduling tables for source requirements and stages results.

ADD r1, r2, r3

1-

ADD r4, r1, r6

2

Wait for r1

LDR r7, [r4]

4

Wait two cycles for r4

Multi-cycle instruction

Multi-cycle instructions must issue in pipeline 0 and can only dual issue in their last iteration.

MOV r1, r2

1-

LDM r3, {r4-r7}

2

Wait for pipeline 0, transfer r4

LDM (cycle 2)

3

Transfer r5, r6

LDM (cycle 3)

4

Transfer r7

ADD r8, r9, r10

4

Dual issue possible on last transfer


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