To start the PLE, the software must program the following registers:
L2 PLE User Accessibility
L2 PLE Channel Number
L2 PLE Control
L2 PLE Internal Start Address
L2 PLE Internal End Address
L2 PLE Context ID.
After the software has programmed the registers, it enables
the PLE by programming the L2 PLE Enable Register with a
start command triggers data to be transferred to
or from the L2 cache RAM as defined by DT bit  of the L2 PLE
Control Register. The internal start address defines the block of
data transfer beginning at the 64-byte aligned address and ending
when the number of cache lines is transferred to or from the L2
cache as defined by the internal end address.
The number of lines is limited to the size of the L2 cache RAM way.
If the direction bit indicates that data is being transferred into the L2 RAM, then the L2 RAM cache way is loaded. However, if the software programmed the direction bit to indicate the transferring of data from the L2 RAM, then each address performs an L2 RAM lookup. Any cache line found to be dirty is evicted from the L2 cache RAM.
It is entirely possible that the L1 data cache contains the same line that is transferred by the PLE engine to the external memory. Therefore it is possible for the line to become valid in the L2 cache as a result of an L1 eviction.
During data transfers into the L2 cache RAM, any L2 cache RAM data present in a different L2 cache RAM way, other than the way specified by the L2 PLE Control Register bits [2:0], remain in the different way. The preload engine continues with the next cache line to be loaded and the line is not relocated to the specified way.
During transfers to or from the L2 cache RAM, if the PLE crosses a page boundary, a hardware translation table walk is performed to obtain a new physical address for that new page. All standard fault checks are also performed. If a fault occurs, the PLE signals an interrupt on error. The PLE updates the L2 PLE Channel Status Register to capture the fault status. The address where the fault occurred is captured in the L2 PLE Internal Start Address Register.
When a PLE channel completes the transfer of the data block to or from the L2 cache RAM, it signals an interrupt. This interrupt can be either secure, nDMASIRQ, or nonsecure, nDMAIRQ, if IC bit  in the L2 PLE Control Register is enabled. In addition, there might be an interrupt-on-error, nDMAEXTERRIRQ, indicated if the PLE aborts for any reason and if the interrupt-on-error bit is enabled.
If you program the PLE to load data into the L2 cache RAM, the PLE transfers data to the L2 cache RAM if the memory region type is cacheable. To determine the memory region type, the PLE performs a hardware translation table walk at the start of the sequence and for any 4KB page boundary. The PLE channel does not save any state for the table walk. The translation procedure is for exception checking purposes and for determination of the memory attributes of the page. Any unexpected L2 cache RAM hits found when using the PLE are ignored for any type of data transfer.
Both channels can run concurrently and be programmed to transfer data from external memory to the same L2 cache RAM way. At the completion of both PLE transactions, the data from either channel 0 or 1might be present in the L2 cache.