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2.17.2. Security Extensions write access disable

The processor pin CP15SDISABLE disables write access to certain registers in the system control coprocessor. Attempts to write to these registers when CP15SDISABLE is HIGH result in an Undefined Instruction exception. Reads from the registers are still permitted. See Chapter 3 System Control Coprocessor for more information about the registers affected by this pin.

A change to the CP15SDISABLE pin takes effect on the instructions decoded by the processor as quickly as practically possible. Software must perform an ISB instruction, after a change to this pin on the boundary of the macrocell, to ensure that its effect is recognized for following instructions. It it is expected that:

  • control of the CP15SDISABLE pin remains within the SoC that embodies the macrocell

  • the CP15SDISABLE pin is cleared to logic 0 by the SoC hardware at reset.

You can use the CP15SDISABLE pin to disable subsequent access to the system control processor registers after the secure boot code runs and protect the configuration that the secure boot code applies.


The register accesses affected by the CP15SDISABLE pin are only accessible in secure privileged modes.

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