The purpose of the Cache Level ID Register is to indicate the cache levels that are implemented. The register indicates the level of unification, LoU, and the level of coherency, LoC. For example, in the CortexA8 processor, the point where both data and instruction are unified is the Level 2 cache, therefore, the LoU is 3'b001. The point where both data and instruction are coherent is the AMBA AXI interface, therefore, the LoC is 3'b010.
The Cache Level ID Register is:
a read-only register common for Secure and Nonsecure states
accessible in privileged modes only.
Figure 3.16 shows the bit arrangement of the Cache Level ID Register.
Table 3.37 shows how the bit values correspond with the Cache Level ID Register functions.
|[29:27]||LoU||3'b001 = level of unification|
|[26:24]||LoC||3'b010 = level of coherency|
|[23:21]||CL 8||3'b000 = no cache at Cache Level (CL) 8|
|[20:18]||CL 7||3'b000 = no cache at CL 7|
|[17:15]||CL 6||3'b000 = no cache at CL 6|
|[14:12]||CL 5||3'b000 = no cache at CL 5|
|[11:9]||CL 4||3'b000 = no cache at CL 4|
|[8:6]||CL 3||3'b000 = no cache at CL 3|
3'b000 = no cache at CL 2
3'b100 = unified cache at CL 2
|[2:0]||CL 1||3'b011 = separate instruction and data cache at CL 1|
Table 3.38 shows the results of attempted access for each mode.
|Secure privileged||Nonsecure privileged||Secure User||Nonsecure User|
 An entry of Undefined in the table means that the access gives an Undefined Instruction exception when the coprocessor instruction is executed.
To access the Cache Level ID Register, read CP15 with:
MRC p15, 1, <Rd>, c0, c0, 1 ; Read Cache Level ID Register