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3.2.24. c0, Cache Size Selection Register

The purpose of the Cache Size Selection Register is to hold the value that the processor uses to select the Cache Size Identification Register to use.

The Cache Size Selection Register is:

  • a read/write register banked for Secure and Nonsecure states

  • accessible in privileged modes only.

Figure 3.19 shows the bit arrangement of the Cache Size Selection Register.

Figure 3.19. Cache Size Selection Register format

Figure 3.19. Cache Size Selection Register format

Table 3.44 shows how the bit values correspond with the Cache Size Selection Register functions.

Table 3.44. Cache Size Selection Register bit functions
[31:4]-Reserved. UNP, SBZ.



Cache level selected

3'b000 = level 1

3'b001 = level 2

3'b010 - 3'b111 = reserved.

[0]InDInstruction (1) or Data/Unified (0).

Table 3.45 shows the results of attempted access for each mode.

Table 3.45. Results of access to the Cache Size Selection Register[22]
Secure privilegedNonsecure privilegedSecure UserNonsecure User
Secure DataSecure DataNonsecure DataNonsecure DataUndefinedUndefinedUndefinedUndefined

[22] An entry of Undefined in the table means that the access gives an Undefined Instruction exception when the coprocessor instruction is executed.

To access the Cache Size Selection Register, read CP15 with:

MRC p15, 2, <Rd>, c0, c0, 0 ; Read Cache Size Selection Register
MCR p15, 2, <Rd>, c0, c0, 0 ; Write Cache Size Selection Register
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