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3.2.9. c0, Debug Feature Register 0

The purpose of Debug Feature Register 0 is to provide information about the debug system for the processor.

The Debug Feature Register 0 is:

  • a read-only register common to the Secure and Nonsecure states

  • accessible in privileged modes only.

Figure 3.6 shows the bit arrangement of the Debug Feature Register 0.

Figure 3.6. Debug Feature Register 0 format

Figure 3.6. Debug Feature Register 0 format

Table 3.16 shows how the bit values correspond with the Debug Feature Register 0 functions.

Table 3.16. Debug Feature Register 0 bit functions
BitsFieldFunction

[31:24]

-

Reserved, RAZ.

[23:20]

Microcontroller debug model - memory-mapped

Indicates support for the microcontroller debug model:

0x0 = Processor does not support the microcontroller debug model - memory-mapped.

[19:16]

Trace debug model - memory-mapped

Indicates support for the trace debug model - memory-mapped:

0x1 = Processor supports the trace debug model - memory-mapped

0x0 = Processor does not support the trace debug model - memory-mapped.[a]

[15:12]

Trace debug model - coprocessor-based

Indicates support for the coprocessor-based trace debug model:

0x0 = Processor does not support the trace debug model - coprocessor.

[11:8]

Core debug model - memory mapped

Indicates support for the memory-mapped debug model:

0x4 = Processor supports the memory mapped debug model.

[7:4]

Secure debug model - coprocessor-based

Indicates support for the secure debug model - coprocessor:

0x0 = Processor does not support the secure debug model - coprocessor.

[3:0]

Core debug model - coprocessor-based

Indicates support for the coprocessor debug model:

0x0 = Processor does not support the coprocessor debug model.

[a] A value of 0x0 indicates that the ETM option is not configured for the processor, see Configurable options


Table 3.17 shows the results of attempted access for each mode.

Table 3.17. Results of access to Debug Feature Register 0[8]
Secure privilegedNonsecure privilegedSecure UserNonsecure User
ReadWriteReadWriteReadWriteReadWrite
DataUndefinedDataUndefinedUndefinedUndefinedUndefinedUndefined

[8] An entry of Undefined in the table means that the access gives an Undefined Instruction exception when the coprocessor instruction is executed.


To access the Debug Feature Register 0, read CP15 with:

MRC p15, 0, <Rd>, c0, c1, 2 ; Read Debug Feature Register 0
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