The purpose of the Instruction Set Attributes Register 0 is to provide information about the instruction set that the processor supports beyond the basic set.
The Instruction Set Attributes Register 0 is:
a read-only register common to the Secure and Nonsecure states
accessible in privileged modes only.
Figure 3.11 shows the bit arrangement of the Instruction Set Attributes Register 0.
Table 3.27 shows how the bit values correspond with the Instruction Set Attributes Register 0 functions.
Indicates support for divide instructions:
Indicates support for debug instructions:
Indicates support for coprocessor instructions. This field reads as zero (RAZ).
Compare and branch instructions
Indicates support for combined compare and branch instructions:
Indicates support for bitfield instructions:
Bit count instructions
Indicates support for bit counting instructions:
Indicates support for atomic load and store instructions:
Table 3.28 shows the results of attempted access for each mode.
|Secure privileged||Nonsecure privileged||Secure User||Nonsecure User|
 An entry of Undefined in the table means that the access gives an Undefined Instruction exception when the coprocessor instruction is executed.
To access the Instruction Set Attributes Register 0, read CP15 with:
MRC p15, 0, <Rd>, c0, c2, 0 ; Read Instruction Set Attributes Register 0