The purpose of the Memory Model Feature Register 3 is to provide information about the memory model, memory management, cache support, and TLB operations of the processor.
The Memory Model Feature Register 3 is:
a read-only register common to the Secure and Nonsecure states
accessible in privileged modes only.
Figure 3.10 shows the bit arrangement of the Memory Model Feature Register 3.
Table 3.25 shows how the bit values correspond with the Memory Model Feature Register 3 functions.
Indicates support for supersections:
|Branch predictor maintenance|
Indicates support for branch predictor maintenance operations:
Hierarchical cache maintenance operations by set and way
Indicates support for invalidate cache by set and way, clean by set and way, and invalidate and clean by set and way:
Hierarchical cache maintenance operations by MVA
Indicates support for invalidate cache by MVA, clean by MVA, invalidate and clean by MVA, and invalidate all:
Table 3.26 shows the results of attempted access for each mode.
|Secure privileged||Nonsecure privileged||Secure User||Nonsecure User|
 An entry of Undefined in the table means that the access gives an Undefined Instruction exception when the coprocessor instruction is executed.
To access the Memory Model Feature Register 3, read CP15 with:
MRC p15, 0, <Rd>, c0, c1, 7 ; Read Memory Model Feature Register 3