The purpose of Processor Feature Register 1 is to provide information about the execution state support and programmer’s model for the processor.
The Processor Feature Register 1 is:
a read-only register common to the Secure and Nonsecure states
accessible in privileged modes only.
Figure 3.5 shows the bit arrangement of the Processor Feature Register 1.
Table 3.14 shows how the bit values correspond with the Processor Feature Register 1 functions.
Microcontroller programmer’s model
Indicates support for microcontroller programmer’s model:
Indicates support for Security Extensions Architecture v1:
Indicates support for standard ARMv4 programmer’s model. All processor operating modes are supported:
Table 3.15 shows the results of attempted access for each mode.
|Secure privileged||Nonsecure privileged||Secure User||Nonsecure User|
 An entry of Undefined in the table means that the access gives an Undefined Instruction exception when the coprocessor instruction is executed.
To access the Processor Feature Register 1, read CP15 with:
MRC p15, 0, <Rd>, c0, c1, 1 ; Read Processor Feature Register 1