The purpose of the Monitor Vector Base Address Register is to hold the base address for the Monitor mode exception vector. See Exceptions for more information.
The Monitor Vector Base Address Register is:
a read/write register in the Secure state only
accessible in secure privileged modes only.
Figure 3.62 shows the bit arrangement of the Monitor Vector Base Address Register.
Table 3.138 shows how the bit values correspond with the Monitor Vector Base Address Register functions.
|[31:5]||Monitor vector base address|
Holds the base address. Determines the location that the core branches to, on a Monitor mode exception. The reset value is 0.
|[4:0]||-||Reserved. UNP, SBZ.|
When an exception branches to the Monitor mode, the core branches to address:
Monitor_Base_Address + Exception_Vector_Address.
The Software Monitor Exception caused by an SMC instruction branches to Monitor mode. You can configure IRQ, FIQ, and External abort exceptions to branch to Monitor mode, see c1, Secure Configuration Register. These are the only exceptions that can branch to Monitor mode and that use the Monitor Vector Base Address Register to calculate the branch address. See Exceptions for more information.
The Monitor Vector Base Address Register is
reset. The secure boot code must program the register with an appropriate
value for the Monitor.
Attempts to write to this register in secure privileged mode when CP15SDISABLE is HIGH result in an Undefined Instruction exception, see Security Extensions write access disable.
Table 3.139 shows the results of attempted access for each mode.
|Secure privileged||Nonsecure privileged||Secure User||Nonsecure User|
 An entry of Undefined in the table means that the access gives an Undefined Instruction exception when the coprocessor instruction is executed.
To access the Monitor Vector Base Address Register, read or write CP15 with:
MRC p15, 0, <Rd>, c12, c0, 1 ; Read Monitor Vector Base Address Register
MCR p15, 0, <Rd>, c12, c0, 1 ; Write Monitor Vector Base Address Register