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3.2.74. c15, L1 system array debug data registers

The purpose of the L1 system array debug data registers is to hold the data:

  • that is returned on instruction side or data side TLB CAM, TLB ATTR, TLB PA, HVAB, tag, data, GHB, and BTB instruction or data side read operations

  • for TLB CAM, TLB ATTR, TLB PA, HVAB, tag, data, GHB, and BTB instruction side or data side write operations.

Because BTB, TLB, and data arrays are greater than 32-bits wide, the processor contains two registers, data low register and data high register, to hold data when retrieving or registering data as a result of read/write operations. If the data is greater than 32-bit wide, both the low and high registers are used to transfer data. Otherwise, only the low register is used to transfer data.

The Data 0 and Data 1 read/write registers are accessible in secure privileged modes only.

To access the L1 system debug registers, read or write CP15 with:

MCR p15, 0, <Rd>, c15, c0, 0 ; Write data L1 Data 0 Register
MRC p15, 0, <Rd>, c15, c0, 0 ; Read data L1 Data 0 Register
MCR p15, 0, <Rd>, c15, c0, 1 ; Write data L1 Data 1 Register
MRC p15, 0, <Rd>, c15, c0, 1 ; Read data L1 Data 1 Register
MCR p15, 0, <Rd>, c15, c1, 0 ; Write instruction L1 Data 0 Register
MRC p15, 0, <Rd>, c15, c1, 0 ; Read instruction L1 Data 0 Register
MCR p15, 0, <Rd>, c15, c1, 1 ; Write instruction L1 Data 1 Register
MRC p15, 0, <Rd>, c15, c1, 1 ; Read instruction L1 Data 1 Register

Figure 3.67 shows the bit arrangement of the L1 Data 0 Register when retrieving or registering data as a result of the read/write operations.

Figure 3.67. Instruction and Data side Data 0 Registers format

Figure 3.67. Instruction and Data side Data 0
Registers format

Figure 3.68 shows the bit arrangement of the L1 Data 1 Register when retrieving or registering data as a result of the read/write operations.

Figure 3.68. Instruction and Data side Data 1 Registers format

Figure 3.68. Instruction and Data side Data 1
Registers format

Table 3.147 shows how the bit values correspond with the I-L1 or D-L1 Data 0 Register functions as a result of a TLB CAM read/write operation.

Table 3.147. Functional bits of I-L1 or D-L1 Data 0 Register for a TLB CAM operation
BitsFieldFunction

[31:0]

Data

Holds TLB CAM information.


Table 3.148 shows how the bit values correspond with the I-L1 or D-L1 Data 1 Register functions as a result of a TLB CAM read/write operation.

Table 3.148. Functional bits of I-L1 or D-L1 Data 1 Register for a TLB CAM operation
BitsFieldFunction
[31:5]-Reserved. UNP, SBZ.
[4:0]Data

Holds TLB CAM information.


To perform a TLB CAM operation, read or write CP15 with:

MCR p15, 0, <Rd>, c15, c0, 2 ; D-L1 CAM write
MCR p15, 0, <Rd>, c15, c2, 2 ; D-L1 CAM read
MCR p15, 0, <Rd>, c15, c1, 2 ; I-L1 CAM write
MCR p15, 0, <Rd>, c15, c3, 2 ; I-L1 CAM read

Table 3.149 shows how the bit values correspond with the I-L1 or D-L1 Data 0 Register functions as a result of a TLB ATTR read/write operation.

Table 3.149. Functional bits of I-L1 or D-L1 Data 0 Register for a TLB ATTR operation
BitsFieldFunction
[31:12]-Reserved. UNP, SBZ.
[11:0]DataHolds TLB ATTR information.

To perform a TLB ATTR operation, read or write CP15 with:

MCR p15 0, <Rd>, c15, c0, 3 ; D-L1 TLB ATTR write
MCR p15 0, <Rd>, c15, c2, 3 ; D-L1 TLB ATTR read
MCR p15 0, <Rd>, c15, c1, 3 ; I-L1 TLB ATTR write
MCR p15 0, <Rd>, c15, c3, 3 ; I-L1 TLB ATTR read

Table 3.150 shows how the bit values correspond with the I-L1 or D-L1 Data 0 Register as a result of a TLB PA array read/write operation.

Table 3.150. Functional bits of I-L1 or D-L1 Data 0 Register for a TLB PA array operation
BitsFieldFunction
[31:29]-Reserved. UNP, SBZ.
[28:0]Data

Holds TLB PA information.


To perform a TLB PA operation, read or write CP15 with:

MCR p15 0, <Rd>, c15, c0, 4 ; D-L1 TLB PA write
MCR p15 0, <Rd>, c15, c2, 4 ; D-L1 TLB PA read
MCR p15 0, <Rd>, c15, c1, 4 ; I-L1 TLB PA write
MCR p15 0, <Rd>, c15, c3, 4 ; I-L1 TLB PA read

Table 3.151 shows how the bit values correspond with the I-L1 or D-L1 Data 0 Register as a result of a HVAB array read/write operation.

Table 3.151. Functional bits of I-L1 or D-L1 Data 0 Register for an HVAB array operation
BitsFieldFunction
[31:8]-Reserved. UNP, SBZ.
[7:0]DataHolds HVAB information.

To perform a HVAB operation, read or write CP15 with:

MCR p15 0, <Rd>, c15, c0, 5 ; D-L1 HVAB write
MCR p15 0, <Rd>, c15, c2, 5 ; D-L1 HVAB read
MCR p15 0, <Rd>, c15, c1, 5 ; I-L1 HVAB write
MCR p15 0, <Rd>, c15, c3, 5 ; I-L1 HVAB read

Table 3.152 shows how the bit values correspond with the I-L1 or D-L1 Data 0 Register as a result of an L1 tag array read/write operation.

Table 3.152. Functional bits of I-L1 or D-L1 Data 0 Register for an L1 tag array operation
BitsFieldFunction
[31:23]-Reserved. UNP, SBZ.
[22:0]DataHolds L1 tag array information.

To perform a tag operation, read or write CP15 with:

MCR p15 0, <Rd>, c15, c0, 6 ; D-L1 tag write
MCR p15 0, <Rd>, c15, c2, 6 ; D-L1 tag read
MCR p15 0, <Rd>, c15, c1, 6 ; I-L1 tag write
MCR p15 0, <Rd>, c15, c3, 6 ; I-L1 tag read

Table 3.153 shows how the bit values correspond with the I-L1 or D-L1 Data 0 Register as a result of an L1 data array read/write operation.

Table 3.153. Functional bits of I-L1 or D-L1 Data 0 Register for L1 data array operation
BitsFieldFunction
[31:0]DataHolds L1 data array information.

Table 3.154 shows how the bit values correspond with the I-L1 or D-L1 Data 1 Register as a result of an L1 data array read/write operation.

Table 3.154. Functional bits of I-L1 or D-L1 Data 1 Register for L1 data array operation
BitsFieldFunction
[30:6]-Reserved. UNP, SBZ.
[5:0]DataHolds L1 data array information.

To perform a data operation on the Data 0 or Data 1 Register, read or write CP15 with:

MCR p15 0, <Rd>, c15, c0, 7 ; D-L1 data write
MCR p15 0, <Rd>, c15, c2, 7 ; D-L1 data read
MCR p15 0, <Rd>, c15, c1, 7 ; I-L1 data write
MCR p15 0, <Rd>, c15, c3, 7 ; I-L1 data read

Table 3.155 shows how the bit values correspond with the I-L1 Data 0 Register as a result of a BTB array read/write operation.

Table 3.155. Functional bits of I-L1 Data 0 Register for a BTB array operation
BitsFieldFunction
[31:0]DataHolds L1 Data 0 Register BTB information

Table 3.156 shows how the bit values correspond with the I-L1 Data 1 Register as a result of a BTB array read/write operation.

Table 3.156. Functional bits of I-L1 Data 1 Register for a BTB array operation
BitsFieldFunction
[31:28]-Reserved. UNP, SBZ.
[27:0]DataHolds L1 Data 1 Register BTB information.

To perform a BTB operation on the Data 0 or Data 1 Register, read or write CP15 with:

MCR p15 0, <Rd>, c15, c5, 3 ; I-L1 BTB write
MCR p15 0, <Rd>, c15, c7, 3 ; I-L1 BTB read

Table 3.157 shows how the bit values correspond with the I-L1 Data 0 Register as a result of a GHB array read/write operation.

Table 3.157. Functional bits of I-L1 Data 0 Register for a GHB array operation
BitsFieldFunction
[31:0]Data

Holds L1 Data 0 Register GHB information


To perform a GHB operation on the Data 0 Register, read or write CP15 with:

MCR p15 0, <Rd>, c15, c5, 2 ; I-L1 GHB write
MCR p15 0, <Rd>, c15, c7, 2 ; I-L1 GHB read
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