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3.2.1. Register allocation

Table 3.3 shows a summary the register allocation and reset values of the system control coprocessor where:

  • CRn is the register number within CP15

  • Op1 is the Opcode_1 value for the register

  • CRm is the operational register

  • Op2 is the Opcode_2 value for the register

  • Security state can be Secure, S, or Nonsecure, NS, and is:

    • B, registers banked in Secure and Nonsecure states. If the registers are not banked then they are common to Secure or Nonsecure states or only accessible in one state.

    • NA, no access

    • RO, read-only access

    • RO, read-only access in privileged modes only

    • R/W, read/write access

    • R/W, read/write access in privileged modes only

    • WO, write-only access

    • WO, write-only access in privileged modes only

    • X, access depends on another register or external signal.

Table 3.3. Summary of CP15 registers and operations
CRnOp1CRmOp2Register or operationSecurity stateReset valuePage
     NSS  
c00c0{0, 4, 6-7}Main ID RORO

0x413FC082

c0, Main ID Register
   1Cache TypeRORO

0x82048004

c0, Cache Type Register
   2TCM TypeRORO0x00000000c0, TCM Type Register
   3TLB TypeRORO0x00202001c0, TLB Type Register
   5Multiprocessor IDRORO0x00000000c0, Multiprocessor ID Register
  c10Processor Feature 0RORO

0x00001131

c0, Processor Feature Register 0
   1Processor Feature 1RORO0x00000011c0, Processor Feature Register 1
   2Debug Feature 0RORO0x00010400 or 0x00000400c0, Debug Feature Register 0
   3Auxiliary Feature 0RORO0x00000000c0, Auxiliary Feature Register 0
   4Memory Model Feature 0RORO

0x01100003

c0, Memory Model Feature Register 0
   5Memory Model Feature 1RORO0x20000000c0, Memory Model Feature Register 1
   6Memory Model Feature 2RORO0x01202000c0, Memory Model Feature Register 2
   7Memory Model Feature 3RORO

0x00000211

c0, Memory Model Feature Register 3
  c20Instruction Set Attribute 0RORO

0x00101111

c0, Instruction Set Attributes Register 0
   1Instruction Set Attribute 1RORO0x13112111 c0, Instruction Set Attributes Register 1
   2Instruction Set Attribute 2RORO

0x21232031

c0, Instruction Set Attributes Register 2
   3Instruction Set Attribute 3RORO0x11112131c0, Instruction Set Attributes Register 3
   4Instruction Set Attribute 4RORO0x00011142c0, Instruction Set Attributes Register 4
   5-7Instruction Set Attribute 5-7RORO0x00000000c0, Instruction Set Attributes Registers 5-7
  c3-c70-7Reserved for Feature ID RegistersRORO0x00000000-
  c8-c150-7Undefined----
 1c00Cache Size Identification ROROUnpredictablec0, Cache Size Identification Registers
  1Cache Level IDRORO0x0A000023 or 0x0A000003c0, Cache Level ID Register
  2-6Undefined ----
  7Silicon IDRORO[a]c0, Silicon ID Register
  c1-c150-7Undefined ----
 2c00Cache Size SelectionR/WR/W, BUnpredictablec0, Cache Size Selection Register
  1-7Undefined----
  c1-c150-7Undefined----
 3-7c0-c150-7Undefined----
c10c00ControlR/WR/W, B[b], X0x00C50078[c]c1, Control Register
   1Auxiliary ControlBB0x00000002c1, Auxiliary Control Register
   2Coprocessor Access ControlR/WR/W0x00000000c1, Coprocessor Access Control Register
   3-7Undefined----
  c10Secure ConfigurationNAR/W0x00000000c1, Secure Configuration Register
   1Secure Debug EnableNAR/W0x00000000c1, Secure Debug Enable Register
   2Nonsecure Access ControlROR/W0x00000000c1, Nonsecure Access Control Register
   3-7Undefined----
  c2-c150-7Undefined----
 1-7c0-c150-7Undefined----
c20c00Translation Table Base 0R/WR/W, B, XUnpredictablec2, Translation Table Base Register 0
   1Translation Table Base 1R/WR/W, BUnpredictablec2, Translation Table Base Register 1
   2Translation Table Base ControlR/WR/W, B, XUnpredictablec2, Translation Table Base Control Register
   3-7Undefined----
  c1-c150-7Undefined----
 1-7c0-c150-7Undefined----
c30c00Domain Access ControlR/WR/W, B, XUnpredictablec3, Domain Access Control Register
   1-7Undefined----
  c1-c150-7Undefined----
 1-7c0-c150-7Undefined----
c40-7c0-c150-7Undefined----
c50c00Data Fault StatusR/WR/W, BUnpredictablec5, Data Fault Status Register
   1Instruction Fault StatusR/WR/W, BUnpredictablec5, Instruction Fault Status Register
   2-7Undefined----
  c10Data Auxiliary Fault StatusR/WR/W, BUnpredictablec5, Auxiliary Fault Status Registers
   1Instruction Auxiliary Fault StatusR/WR/W, BUnpredictablec5, Auxiliary Fault Status Registers
  c12-7Undefined----
  c2-c150-7Undefined----
 1-7c0-c150-7Undefined----
c60c00Data Fault AddressR/WR/W, BUnpredictablec6, Data Fault Address Register
   1Undefined----
   2Instruction Fault AddressR/WR/W, BUnpredictablec6, Instruction Fault Address Register
   3-7Undefined----
  c1-c150-7Undefined----
 1-7c0-c150-7Undefined----
c70c00-3Undefined----
   4NOP (WFI)WOWO-About the system control coprocessor
   5-7Undefined----
  c1-c30-7Undefined----
  c40Physical AddressR/WR/W, B0x00000000PA Register
   1-7Undefined----
  c50Invalidate all instruction caches to point of unificationWOWO-c7, Cache operations
   1Invalidate instruction cache line to point of unificationWOWO-c7, Cache operations
   2-3Undefined----
   4Flush Prefetch BufferWOWO-c7, Cache operations
   5Undefined----
   6NOP (Invalidate entire branch predictor array)WOWO-About the system control coprocessor
   7NOP (Invalidate branch predictor array line by MVA)WOWO-About the system control coprocessor
  c60Undefined----
   1Invalidate data cache line to point of coherency by MVAWOWO-c7, Cache operations
   2Invalidate data cache line by set and wayWOWO-c7, Cache operations
   3-7Undefined----
  c70-7Undefined----
  c80-3VA to PA translation in the current stateWOWO-VA to PA translation in the current Secure or Nonsecure state
   4-7VA to PA translation in the other stateNAWO-VA to PA translation in the other Secure or Nonsecure state
  c90-7Undefined----
  c100Undefined----
   1Clean data cache line to point of coherency by MVAWOWO-c7, Cache operations
   2Clean data cache line by set and wayWOWO-c7, Cache operations
   3Undefined----
   4Data Synchronization BarrierWOWO-Data synchronization barrier operation
   5Data Memory BarrierWOWO-Data memory barrier operation
   6-7Undefined----
  c110Undefined----
   1Clean data cache line to point of unification by MVAWOWO-c7, Cache operations
   2-7Undefined----
  c12-c130-7Undefined----
  c140Undefined----
   1Clean and invalidate data cache line to point of coherency by MVAWOWO-c7, Cache operations
   2Clean and invalidate data cache line by set and wayWOWO-c7, Cache operations
   3-7Undefined----
  c150-7Undefined----
 1-7c0-c150-7Undefined----
c80c0-c40-7Undefined----
  c50Invalidate Instruction TLB unlocked entriesWOWO, B-c8, TLB operations
   1Invalidate Instruction TLB entry by MVAWOWO, B-c8, TLB operations
   2Invalidate Instruction TLB entry on ASID matchWOWO, B-c8, TLB operations
   3-7Undefined----
  c60Invalidate Data TLB unlocked entriesWOWO, B-c8, TLB operations
   1Invalidate Data TLB entry by MVAWOWO, B-c8, TLB operations
   2Invalidate Data TLB entry on ASID matchWOWO, B-c8, TLB operations
   3-7Undefined----
  c70Invalidate unified TLB unlocked entriesWOWO, B-c8, TLB operations
   1Invalidate unified TLB entry by MVAWOWO, B-c8, TLB operations
   2Invalidate unified TLB entry on ASID matchWOWO, B-c8, TLB operations
   3-7Undefined----
  c8-c150-7Undefined----
 1-7c0-c150-7Undefined----
c90c0-c110-7Undefined----
  c120Performance Monitor ControlR/W, XR/W, X0x41002000c9, Performance Monitor Control Register
   1Count Enable Set R/W, XR/W, X0x00000000c9, Count Enable Set Register
   2Count Enable Clear R/W, XR/W, X0x00000000c9, Count Enable Clear Register
   3Overflow Flag Status R/W, XR/W, X0x00000000c9, Overflow Flag Status Register
   4Software Increment R/W, XR/W, X0x00000000c9, Software Increment Register
   5Performance Counter Selection R/W, XR/W, XUnpredictablec9, Performance Counter Selection Register
   6-7Undefined----
  c130Cycle Count R/W, XR/W, X0x00000000c9, Cycle Count Register
   1Event Selection R/W, XR/W, XUnpredictablec9, Event Selection Register
   2Performance Monitor CountR/W, XR/W, X0x00000000c9, Performance Monitor Count Registers
   3-7Undefined----
  c140User Enable R/WR/W0x00000000c9, User Enable Register
   1Interrupt Enable Set R/WR/W0x00000000c9, Interrupt Enable Set Register
   2Interrupt Enable Clear R/WR/W0x00000000c9, Interrupt Enable Clear Register
   3-7Undefined----
  c150-7Undefined----
 1c00L2 Cache LockdownR/WR/W0x00000000c9, L2 Cache Lockdown Register
   1Undefined----
   2L2 Cache Auxiliary Control ROR/W0x00000042c9, L2 Cache Auxiliary Control Register
   3-7Undefined----
  c1-c150-7Undefined----
 2-7c0-c150-7Undefined----
c100c00Data TLB Lockdown RegisterR/WR/W0x00000000c10, TLB Lockdown Registers
   1Instruction TLB Lockdown RegisterR/WR/W0x00000000c10, TLB Lockdown Registers
   2-7Undefined----
  c10Data TLB PreloadWOWO-c10, TLB preload operation
   1Instruction TLB PreloadWOWO-c10, TLB preload operation
   2-7Undefined----
  c20Primary Region Remap RegisterR/WR/W, B, X0x00098AA4c10, Memory Region Remap Registers
   1Normal Memory Remap RegisterR/WR/W, B, X0x44E048E0c10, Memory Region Remap Registers
   2-7Undefined----
  c3-c150-7Undefined----
 1-7c0-c150-7Undefined----
c110c00PLE Identification and StatusRO, XRO0x00000003[d]c11, PLE Identification and Status Registers
   1Undefined----
   2-3PLE Identification and StatusRO, XRO0x00000000[d]c11, PLE Identification and Status Registers
   4-7Undefined----
  c10PLE User AccessibilityR/W, XR/W0x00000000c11, PLE User Accessibility Register
   1-7Undefined----
  c20PLE Channel NumberR/W, XR/W, XUnpredictablec11, PLE Channel Number Register
   1-7Undefined----
  c30-2PLE enableWO, XWO, X-c11, PLE enable commands
   3-7Undefined----
  c40PLE ControlR/W, XR/W, XUnpredictablec11, PLE Control Register
   1-7Undefined----
  c50PLE Internal Start AddressR/W, XR/W, XUnpredictablec11, PLE Internal Start Address Register
   1-7Undefined----
  c60-7Undefined----
  c70PLE Internal End AddressR/W, XR/W, XUnpredictablec11, PLE Internal End Address Register
   1-7Undefined----
  c80PLE Channel StatusRO, XRO, X0x00000000c11, PLE Channel Status Register
   1-7Undefined----
  c9-140-7Undefined----
  c150PLE Context IDR/W, XR/WUnpredictablec11, PLE Context ID Register
c110c151-7Undefined----
 1-7c0-c150-7Undefined----
c120c00Secure or Nonsecure Vector Base AddressR/WR/W, B, X0x00000000c12, Secure or Nonsecure Vector Base Address Register
   1Monitor Vector Base AddressNAR/W, X0x00000000c12, Monitor Vector Base Address Register
   2-7Undefined----
  c10Interrupt StatusRORO0x00000000[e]c12, Interrupt Status Register
   1-7Undefined----
  c2-150-7Undefined----
 1-7c0-150-7Undefined----
c130c00FCSE PIDR/WR/W, B, X0x00000000c13, FCSE PID Register
   1Context IDR/WR/W, BUnpredictablec13, Context ID Register
   2User read/write Thread and Process IDR/WR/W, BUnpredictablec13, Thread and Process ID Registers
   3User read-only Thread and Process IDR/W, ROR/W, RO, B[f]Unpredictablec13, Thread and Process ID Registers
   4Privileged only Thread and Process IDR/WR/W, BUnpredictablec13, Thread and Process ID Registers
   5-7Undefined----
  c1-c150-7Undefined----
 1-7c0-c150-7Undefined----
c140-7c0-c150-7Undefined----
c150c00D-L1 Data 0 RegisterNAR/WUnpredictablec15, L1 system array debug data registers
   1D-L1 Data 1 RegisterNAR/WUnpredictablec15, L1 system array debug data registers
   2D-TLB CAM write operationNAWO-c15, L1 TLB operations
   3D-TLB ATTR write operationNAWO-c15, L1 TLB operations
   4D-TLB PA write operationNAWO-c15, L1 TLB operations
   5D-HVAB write operationNAWO-c15, L1 HVAB array operations
   6D-Tag write operationNAWO-c15, L1 tag array operations
   7D-Data write operationNAWO-c15, L1 data array operations
  c10I-L1 Data 0 RegisterNAR/WUnpredictablec15, L1 system array debug data registers
   1I-L1 Data 1 RegisterNAR/WUnpredictablec15, L1 system array debug data registers
   2I-TLB CAM write operationNAWO-c15, L1 TLB operations
   3I-TLB ATTR write operationNAWO-c15, L1 TLB operations
   4I-TLB PA write operationNAWO-c15, L1 TLB operations
   5I-HVAB write operationNAWO-c15, L1 HVAB array operations
   6I-Tag write operationNAWO-c15, L1 tag array operations
   7I-Data write operationNAWO-c15, L1 data array operations
  c20-1Undefined----
   2D-TLB CAM read operationNAWO-c15, L1 TLB operations
   3D-TLB ATTR read operationNAWO-c15, L1 TLB operations
   4D-TLB PA read operationNAWO-c15, L1 TLB operations
   5D-HVAB read operationNAWO-c15, L1 HVAB array operations
   6D-Tag read operationNAWO-c15, L1 tag array operations
   7D-Data read operationNAWO-c15, L1 data array operations
  c30-1UndefinedNA---
   2I-TLB CAM read operationNAWO-c15, L1 TLB operations
   3I-TLB ATTR read operationNAWO-c15, L1 TLB operations
   4I-TLB PA read operationNAWO-c15, L1 TLB operations
   5I-HVAB read operationNAWO-c15, L1 HVAB array operations
   6I-Tag read operationNAWO-c15, L1 tag array operations
   7I-Data read operationNAWO-c15, L1 data array operations
  c40-7Undefined----
  c50-1Undefined----
   2GHB write operationNAWO-c15, GHB array operations
   3BTB write operationNAWO-c15, BTB array operations
   4-7Undefined----
  c60-7Undefined----
  c70-1Undefined----
   2GHB read operationNAWO-c15, GHB array operations
   3BTB read operationNAWO-c15, BTB array operations
   4-7Undefined----
  c80L2 Data 0 RegisterNAR/WUnpredictablec15, L2 system array debug data registers
   1L2 Data 1 RegisterNAR/WUnpredictablec15, L2 system array debug data registers
   2L2 tag, L2 valid write operationNAWO-c15, L2 tag array operations
   3L2 data, L2 dirty write operationNAWO-c15, L2 tag array operations
   4L2 parity and ECC write operationNAWO-c15, L2 parity/ECC array operations
   5L2 Data 2 RegisterNAR/WUnpredictablec15, L2 system array debug data registers
   6-7Undefined----
  c90-1Undefined----
   2L2 tag, L2 valid read operationNAWO-c15, L2 tag array operations
   3L2 data, L2 dirty read operationNAWO-c15, L2 tag array operations
   4L2 parity and ECC read operationNAWO-c15, L2 parity/ECC array operations
   5-7Undefined----
  c10-c150-7Undefined----
 1-7c0-c150-7Undefined----

[a] Reset value depends on external signals, that is, SILICONID[31:0].

[b] Some bits in this register are banked and some are secure modify only.

[c] Reset value depends on external signals, that is, VINITHI, CFGTE, and CFGNMFI. The value shown in this table assumes these signals are set to zero.

[d] Reset value depends on the number of PLE channels implemented.

[e] Reset value depends on external signals, that is, nFIQ and nIRQ. The value shown in this table assumes these signals are set to zero.

[f] This register is read/write in privileged modes and read-only in User mode.


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