The processor has the following features to support unaligned and mixed-endian data access:
permanently enabled support for unaligned data access
architecturally defined unaligned word, unaligned halfword, and word-aligned doubleword access
byte-reverse instructions that operate on general-purpose register contents to support signed and unsigned halfword data values
separate endianness control for data with instructions fixed as little-endian format, naturally aligned, but with legacy support for 32-bit word-invariant binary images and ROM
EE bit in CP15 c1 Control Register 1 that controls load and store endianness during exceptions
ARM and Thumb instructions to change the endianness and the E flag in the Program Status Registers (PSRs)
byte-invariant addressing to support fine-grain big-endian and little-endian shared data structures, to conform to a shared memory standard.
Instructions are always little-endian and must be aligned according to the size of the instruction:
32-bit ARM instructions must be word-aligned with address bits [1:0] equal to b00.
16-bit or 32-bit Thumb instructions must be halfword-aligned with address bit  equal to 0.